1. Field of the Invention
The present invention relates to tape bonding and testing of integrated circuits utilizing multi-layer testing tape and single-layer lead frame tape having integral bonding bumps and the method of manufacture of such lead frames.
2. Description of the Prior Art
In the interconnection of integrated circuit chips by the tape bonding approach, a number of conductive leads are bonded to the chip at appropriate points for suitable electrical connection to a hybrid substrate, for example. Because of the extremely small size of integrated circuits, the conductive leads are usually manufactured in what may be termed a lead frame configuration. This configuration is an elongated conductive tape having a row of registration or sprocket openings along one or both edges with a number of spaced lead frames positioned along the tape relative to the openings and between the rows. Each frame includes spaced metallic leads that are integral at one end with its frame and project inwardly in the same plane in numbers and direction for the inner free ends of the leads to register with and engage bonding pads on the chips. The chips may be positioned by any standard machine in the frames and bonded to the inner free ends of the leads thereof. With this tape bonding approach the chips may be then tested using a separate multi-layer test tape that provides proper lead isolation.
This single layer metallic lead frame tape is by its very nature simple to manufacture when compound to the conventional multi-layered lead frame tape. However, the multi-layered tape has isolated leads that permit testing of the chip subsequent to bonding; whereas the leads of the single layer tape are shorted together and require an isolation step in the event the chips are to be tested.
It is preferable for many applications, that the inner or free end of each of the leads of a lead frame of the tape or strip have a thicker spot than the remainder of the lead. Such thicker or raised portions are referred to as bonding bumps, and are compressed in contact at an elevated temperature with the appropriate bonding pads of an integrated circuit chip. The bonding machine simultaneously bonds the leads securely to the circuit chip bonding pads. In manufacturing such lead frame strips having the integral raised bonding bumps, it is desirable to spray etch the strip of metal foil that constitutes the tape on both sides simultaneously to produce the desired configuration. In such etching, both sides of the metal foil are protected with photoresist which is imaged with appropriate art work. The features of the art work pattern or image on one side of the foil strip must accurately register with its corresponding features on the opposite side of the foil strip to within several tenths of a mil; and any misalignment or excessive tolerance results in a defective tape.
To prevent any misalignment that would render the lead from tape defective, the manner in which the necessary art work is prepared and utilized is critical. Also, because of the increasing miniaturization of integrated circuits, problems may be encountered in using standard photolithographic techniques. For example, lens distortion in reducing the size of the art work to the actual size required for the lead frame may result in excessive misalignment, particularly where the bonding bumps are integral with the free ends of each of the individual leads of the frame. Also, once the lead frame tapes are manufactured, such extreme miniaturization also requires accurate alignment of the chip with the bonding bumps on the leads of the frame for the actual bonding process, which is difficult to achieve uniformly.
Once the leads of each frame are bonded via their integral bonding bumps to the bonding pads of the IC chip, it is desirable to test the chips prior to incorporation in its ultimate circuit. With the single layer foil tape described thus far this is not possible since all the leads are shorted together. Testing must be done on a tape which is constructed such that the leads are supported by an insulating carrier to provide electrical isolation. This type of tape is more difficult to make, especially with integral lead bonding bumps, since multiple etching steps are required, i.e. for etching the metal and etching the insulating carrier.
Although lead frames, wherein each etched conductive lead has a single, deformable bonding bump on the free end thereof, is satisfactory for bonding to the pads of most IC circuit chips, they do not appear to be satisfactory where the bonding bumps on extremely small bonding pads of the chip are very closely spaced. For example, if the leads are cantilevered for long distances such as fifty times their width, then they may bend so that the array of bonding bumps on the leads will no longer register with the corresponding array of bonding pads on the chip. Also, spray etching of such fine cantilevered leads is difficult because the force of the spray may bend the leads. Further, slight variations in the widths of the fine line leads of the frame due to etching tolerances produce leads of varying impedances. It is desirable to provide a method of testing and a test tape configuration that does not require customizing for each different chip and may be used repeatedly for testing increasingly larger sized chips.